IC-Mart Your Trusted Source for EEPLD – Electronically Erasable Programmable Logic Devices Chips

(from leading manufacturers)

Global Mainstream Manufacturers

1. Microchip Technology

Series / Category	Typical Models	Key Features
SPLD (Simple Logic)	ATF16V8B, ATF22V10C	Industry-standard 20/24-pin; replaces PAL/GAL devices.
High-Density CPLD	ATF1502AS, ATF1504AS, ATF1508AS	Supports 32-128 macrocells; features ISP (In-System Programming).
Low-Voltage Version	ATF16LV8C, ATF22LV10C	Designed for 3.3V systems; ideal for low-power applications.
High-Performance Special	ATF750C, ATF2500C	High gate count (up to 2500); suitable for complex bus interfaces.

2. Altera / Intel

Series Name	Typical Models	Key Features
MAX V (Current Mainstream)	5M40Z, 5M80Z, 5M160Z	Non-volatile; low static power; integrated flash and oscillator.
MAX II	EPM240, EPM570, EPM1270	Flash-based architecture; “instant-on”; high I/O density.
MAX 3000A (Legacy)	EPM3032A, EPM3064A	Traditional EEPROM technology; 5V tolerance (maintenance only).

3. Lattice Semiconductor

Series Name	Typical Models	Key Features
MachXO2 / XO3	LCMXO2-256, LCMXO3L-1300	“Instant-on” FPGA/CPLD hybrid; ultra-low power consumption.
ispMACH 4000V	LC4032V, LC4064V, LC4128V	Pure high-performance CPLD architecture; ultra-fast clock speeds.

4. AMD / Xilinx

Series Name	Typical Models	Key Features
XC9500XL	XC9536XL, XC9572XL, XC95144XL	3.3V EEPROM architecture; 5V tolerant I/O; high performance.
CoolRunner-II	XC2C32A, XC2C64A	Ultra-low power (DataGate technology); ideal for battery-powered devices.

5. Renesas

Series Name	Typical Models	Key Features
GreenPAK 4/5/6	SLG46120, SLG46531, SLG46826	Ultra-small package (from 1mm²); mixed-signal (includes comparators, ADCs).

Leading Chinese Manufacturers and Models

1. Core Manufacturers and Product Lines

Manufacturer	Typical Series	Typical Models	Technical Features
Anlogic	ELF Series	EF1L15, EF2L45, EF3L90	Integrated Flash; CPLD “instant-on” with FPGA logic resources.
Gowin	LittleBee Series	GW1N-1, GW1N-9, GW1NZ-1	Non-volatile FPGA; widely replaces traditional CPLDs. NZ series focuses on ultra-low power.
PangoMicro	Compa Series	PGC1K, PGC2K, PGC7K	Designed for control planes; low cost/power; supports various packages.
BestE	Sealion Series	BSL-1, BSL-2	Focused on small-to-midscale logic; high compatibility; ideal for I/O expansion.
Hercules	M5 Series	M5C06N3L144, M5C02	Flash-based; high-performance non-volatile logic; large user flash memory.

2. Specialized and Niche Players

Beyond general-purpose chips, these firms excel in high-reliability or legacy replacement:

• Fudan Microelectronics: Models include JFM7064, JFM7128. Strong in high-reliability sectors. Architectures are compatible with Altera MAX series for industrial and specialty equipment.
• Chengdu Huasheng (HWCPLD): Focuses on high-performance, high-reliability logic. Provides domestic alternatives to Xilinx XC9500 or legacy Altera series.
• I-Core (AiP): Models include AiP16V8, AiP22V10. Targets SPLD markets; produces 16V8 and 22V10 compatible chips for level shifting and decoding.

---

Core Characteristics: Why “Electronically Erasable”?

Early programmable logic (like UV-EPROM) required ultraviolet light for erasure. This was inconvenient for debugging. EEPLD – Electronically Erasable Programmable Logic Devices solved this:

• Non-volatile: Logic is retained when power is lost. The chip runs instantly upon power-up—no external Flash loading required (unlike most FPGAs).
• In-System Programming (ISP): Update logic directly on the circuit board via data lines. No need to remove the chip. This accelerates prototyping and field updates.
• High Integration: One EEPLD replaces dozens or hundreds of discrete 74-series logic gates.

Typical EEPLD Use Cases

EEPLDs are widely used in industrial, telecom, and consumer electronics due to their “instant-on” capability and moderate logic density.

1. Logic Glue & Interface Translation: The “universal translator” of circuits. They bridge mismatched voltage levels or protocols between a CPU and peripherals.
2. Industrial Automation: Handles complex timing and hardware interlocking in heavy machinery, like concrete pumps or automated assembly lines.
3. Power Management & Reset: Manages power-up sequences for large systems (servers, base stations) before the main CPU or FPGA initializes.
4. I/O Expansion: Expands general-purpose input/output pins when a microcontroller (MCU) runs out of ports.
5. Address Decoding: Quickly identifies CPU address signals to activate specific memory or peripheral devices.

Classification of EEPLDs

1. By Logic Density (Macrocells/Gate Count)

• Low-Density (8-10 Macrocells): Replaces simple logic gates or performs basic decoding. (Example: ATF16V8B).
• High-Density (128+ Macrocells): CPLD-like architecture for complex timing and combinational logic. (Example: ATF1508AS).

2. By Speed and Propagation Delay (t_{PD})

• High-Speed (5ns – 7.5ns): For strict timing in high-speed communication or bus interfaces.
• Standard (15ns – 30ns): For general industrial control and low-speed peripheral protocols.

3. By Power and Voltage

• Zero/Quarter Power: Designed for battery-powered or heat-sensitive systems. Often 3.3V to 5V compatible.
• Standard Power: Typically 5V; used in embedded boards where power consumption is not a primary constraint.

4. By Package and I/O Scale

• Low Pin Count (20-24 pins): Through-hole (PDIP) or small surface mount (SOIC) for simple designs.
• High-Density (80-100+ pins): Large I/O counts (e.g., TQFP-100) for complex system-on-chip integration.